The present generally relates to semiconductor devices and more particularly to a miniaturized high-speed semiconductor device and a fabrication process thereof.
With the development in the art of device miniaturization, the operational speed of field-effect semiconductor devices such as a MOS transistor is increasing every year. On the other hand, such an extremely miniaturized semiconductor device tends to suffer from the problem of so-called short-channel effect, which appears conspicuously in such a miniaturized device having a short gate length, due to the deviation from the classical gradual channel approximation model. When a short-channel effect appears, there arise problems such as deviation of threshold voltage. In the worst case, the drain current becomes no longer controllable by the gate voltage.
Thus, it has been practiced in conventional miniaturized field effect semiconductor devices to reduce the thickness of diffusion regions as small as possible in correspondence to the reduced gate length of the device.
As such an extremely shallow diffusion region tends to cause a problem of increased resistance, it is proposed to provide a layer of low-resistance silicide such as CoSi2 on the surface of the diffusion region by conducting a self-aligned process. See for example Japanese Laid-Open Patent Publication 7-115198.
Meanwhile, there is proposed a process of forming an extremely miniaturized semiconductor device that includes a self-aligned contact structure. See for example Japanese Laid-Open Patent Publication 8-274278.
FIGS. 1A-1H show the foregoing conventional process of forming a self-aligned contact structure.
Referring to FIG. 1A, a gate oxide film 2 and a field oxide film 2A are formed on a p-type Si substrate 1, and a polysilicon layer 3 is deposited on the structure of FIG. 1A in the step of FIG. 1B. The polysilicon layer 3 thus deposited is then doped to the n+-type by an ion-implantation of P+ ions and patterned in the step of FIG. 1C to form a gate electrode 3A. In the step of FIG. 1C, an ion implantation process of As+ is further conducted while using the gate electrode 3A as a mask, to form shallow diffusion regions 1A and 1B of the n+-type at both lateral sides of the gate electrode 3A by a self-alignment process.
Next, in the step of FIG. 1D, an SiO2 film is deposited on the structure of FIG. 1C uniformly by a CVD process, followed by an anisotropic etching process acting substantially perpendicularly to the surface of the substrate 1 to form side wall oxide films 3a and 3b on both side walls of the gate electrode 3A. Further, additional diffusion regions 1C and 1D are formed so as to partially overlap the diffusion region 1A or 1B by conducting an ion-implantation process of As+ while using the gate electrode 3A and the side-wall oxide films 3a and 3b as a mask, to form a so-called LDD (lightly doped drain) structure.
Next, in the step of FIG. 1E, an SiN film 4 is deposited uniformly on the structure of FIG. 1D by a CVD process or a sputtering process, followed by the step of FIG. 1F in which an interlayer insulation film 5 of SiO2, PSG or BPSG is deposited on the foregoing SiN film 4. The interlayer insulation film 5 is further formed with a contact hole 5A in correspondence to the diffusion region 1C by an anisotropic dry etching process. Similarly, a contact hole 5B is formed in the insulation film 5 in correspondence to the diffusion region 1D. The contact hole 5A or 5B may be formed with a size sufficiently larger than the size of the corresponding diffusion region 1C or 1D and can be formed easily by a photolithography without experiencing a difficulty of resolution limit, which generally arises when forming a deep contact hole.
The dry etching process for forming the contact holes 5A and 5B stops spontaneously upon the exposure of the underlying SiN layer 4 as indicated in FIG. 1F. Thus, a step of FIG. 1G is conducted for removing the exposed SiN film 4 by an etching process. Further, a step of FIG. 1H is conducted for removing a part of the gate oxide film 2 that is now exposed at the bottom of the contact holes 5A and 5B, by conducting a selective etching process with respect to the Si substrate 1. As a result of the step of FIG. 1H, minute openings 1c and 1d respectively exposing the diffusion regions 1C and 1D are formed.
It should be noted that the opening 1c is defined by the field oxide film 2A and the side wall oxide film 3a. Similarly, the opening 1d is defined by the other field oxide film 2A and the side wall oxide film 3b. In other words, the openings 1c and 1d are formed in a self-aligned manner, without using a mask process. This means that the openings 1c and 1d can be formed reliably and with reproducibility without restrained from the problem of resolution limit of exposure even when the semiconductor device is extremely miniaturized. Further, as explained already, it is not necessary to miniaturize the contact holes 5A and 5B. Thus, the photolithography for forming the contact holes 5A and 5B can be conducted easily.
Thus, the foregoing self-aligned process of FIGS. 1A-1H is advantageous for forming extremely miniaturized semiconductor devices. As already noted, it is desired in such extremely miniaturized high-speed semiconductor devices to form a low-resistance silicide layer on the surface of the diffusion regions 1C and 1D so as to compensate for the unwanted increase of the resistance, which tends to occur in such extremely shallow diffusion regions.
One possibility of forming such a silicide layer may include the steps of: removing the gate oxide film 2 for the part covering the diffusion regions 1C and 1D; depositing a metal layer of Co or Ti on the exposed surface of the diffusion regions 1C and 1D; and forming a silicide in a self-aligned manner by causing a reaction between the metal layer and the diffusion region. The remaining metal layer may be removed by an etching process. See for example the process disclosed in the Japanese Laid-Open Patent Publication 7-115198.
In such a conventional process of forming a silicide layer, however, there is a substantial risk that the etching process, used in the step of FIG. 1G for removing the SiN film 4 from the bottom of the contact holes 5A and 5B, may proceed further to the diffusion region 1C or 1D and cause a damage thereto.
In order to be sure that such a damage is not to be caused, it is necessary to deposit another SiO2 film in the step of FIG. 1E before depositing the SiN film 4, as an etching stopper. It should be noted that the additional SiO2 film acts as an etching stopper for the etching process employed for removing the SiN film 4, and the problem of damaging of the diffusion region 1C or 1D is positively eliminated. Further, such an additional Si2 film can be easily removed by a selective etching process without causing a damage to the diffusion region 1C or 1D.
It is generally practiced to form such an SiO2 etching stopper layer by a CVD process. In the case of the a semiconductor device in which the silicide layer is formed on the surface of a shallow diffusion region, however, there is a substantial risk that the metal elements constituting the silicide may cause a diffusion and reach the Si substrate because of the high deposition temperature employed in the CVD process. Thus, it has been necessary to form the additional SiO2 film by using a plasma CVD process at a low temperature of typically about 500° C. or less.
On the other hand, the SiO2 etching stopper film thus deposited at a low temperature plasma CVD process tends to contain H2O therein. As the SiO2 etching stopper is covered by the SiN film 4 in the step of FIG. 1G, it is difficult for the H2O molecules in the SiO2 etching stopper film to escape therefrom once covered by the SiN film 4. Thereby, the H2O molecules tend to be confined in the SiO2 film in the form of OH and H ions. It should be noted that the OH ions in the SiO2 etching stopper film, when reached to a region close to the gate oxide film 2 by way of diffusion, may form a surface state which captures electrons.
FIG. 2 shows an example of the self-aligned contact structure that uses an SiO2 etching stopper film, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2, there is provided an etching stopper film 6 of SiO2 on the gate oxide film 2 by a low temperature plasma CVD process such that the SiO2 film 6 covers the gate electrode 3A including the side wall oxide films 3a and 3b. Further, the SiN film 4 is provided so as to cover the SiO2 film 6.
In such a structure, the escaping of H2O from the SiO2 film 6 is difficult as already noted, due to the existence of the SiN film 4 covering the SiO2 film 6. Thus, there is a substantial risk that the OH ions confined in the SiO2 film 6 cause a diffusion toward the interface between the gate oxide film 2 and the Si substrate 1. As noted already, the OH ions thus reached the foregoing interface may form a surface state that captures electrons, particularly the hot electrons created in the channel region right underneath the gate electrode 3A. The capturing of the hot electrons by the surface state may in turn cause an unwanted shift of threshold voltage of the semiconductor device.
It should be noted that the self-aligned contact structure of FIGS. 1A-1H may also be used in a high-speed semiconductor memory device that has a so-called local interconnection structure such as SRAM. In the semiconductor device having such a local interconnection structure, there tends to occur a reaction between the metal layer forming the local interconnection structure and a silicide that is formed on the surface of the diffusion region. In order to avoid the foregoing problem, it is necessary to conduct the deposition of the etching stopper film 6 at a low temperature. However, such a low temperature deposition of the SiO2 etching stopper film 6 causes the problem explained above.